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Alif Semiconductor /AE512F80F55D5AS_CM55_HP_View /I3C /I3C_HW_CAPABILITY

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Interpret as I3C_HW_CAPABILITY

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DEVICE_ROLE_CONFIG 0 (HDR_DDR_EN)HDR_DDR_EN 0 (Val_0x0)HDR_TS_EN 0CLOCK_PERIOD0 (DMA_EN)DMA_EN 0 (SLV_HJ_CAP)SLV_HJ_CAP 0 (SLV_IBI_CAP)SLV_IBI_CAP

HDR_TS_EN=Val_0x0

Description

Hardware Capability Register

Fields

DEVICE_ROLE_CONFIG

The value of field bit defines the configured role of I3C.

3 (Val_0x3): Secondary Master
HDR_DDR_EN

The value of this bit defines the I3C capability to perform HDR-DDR transfers.

1 (Val_0x1): HDR-DDR supported
HDR_TS_EN

The value of this bit defines the I3C capability to perform HDR-TS transfers.

0 (Val_0x0): HDR-TS not supported
CLOCK_PERIOD

The value of this field defines the minimum period of CORE_CLK, that is, the maximum frequency of CORE_CLK that is intended to be fed to I3C.
DMA_EN

The value of this bit defines whether the I3C is configured to have DMA handshaking interface.
SLV_HJ_CAP

The value of this bit defines the slave’s capability to initiate Hot-Join request.
SLV_IBI_CAP

The value of this bit defines the slave’s capability to initiate slave interrupt requests.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data